The present invention relates in general to data processing systems, and in particular, to circuitry for detecting when a delay locked or phase locked loop is in a locked or unlocked condition.
The use of phase locked loops (PLLs) or delay locked loops (DLLs) is common for clock synthesis and synchronization. These sophisticated analog circuits lock to an incoming reference frequency signal and thus provide a synthesized and synchronized clock for use in many applications such a communications, digital processing, microprocessing, etc. Phase locking is a dynamic process that begins when an input data signal is applied to a phase locking circuit. A reference signal is the other input to the phase locking circuit. When the input data signal is applied, an error signal is generated which is applied to a feedback correction circuit that operates to reduce the value of the error signal. A phase locked loop circuit, like any feedback circuit, has a characteristic response that is determined by the values of circuit elements. Typical of feedback circuits, it takes some time for the circuit to stabilize to an acceptable error condition. For a phase locked loop the circuit would stabilize at an acceptable phase error and after stabilization the synchronization will remain locked provided the input data signal does not change at a rate outside the dynamics of the particular circuit. The lock time of a typical PLL may vary three to four times from a best to a worst case determined by variables comprising temperature, power supply, etc. Because of this variation, for applications using a PLL without a lock indicator, the longest possible lock time is used to insure that the PLL has acquired a lock condition. In a noisy environment, the lock point could be missed, and the PLL potentially could require two or three times a typical lock time xe2x80x9csearchingxe2x80x9d for the lock point. Because of these considerations designers specify a very inflated lock time and thus may cause degradation to a system""s performance. There is a need for a lock indication method for PLLs or DLLs that will reduce lock time and give a reliable indication when a phase locked loop is locked.
The present invention employs a circuit that generates a pulse with a width proportional to the phase error between two signals and a pulse when the lagging signal occurs. As the two signals approach phase lock the two pulses become approximately equal. Another similar circuit generates pulses of fixed width dependent on delay elements on each positive edge of the two signals generating a window signal. When the two signals approach phase lock, the pulses generated by the phase detector will fall within the window signal and will have a phase error dependent on the delay of the delay element. Logic that ANDs the phase detector pulse and the window pulse generates a phase lock signal. Additional circuits generate a phase lock indicator if the phase lock signal is true for a number of consecutive transitions of the reference signal. Likewise a phase lock indication is generated if after a phase lock indication the phase lock signal is false for a number of consecutive transitions of the reference signal. In this manner, noise transients and other spurious signals are masked preventing false indications of phase lock or unlock on two signals.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.